1. Field of the Invention
The present invention relates to a programmable controller used in industrial apparatuses, in which operation conditions of a CPU unit are monitored by an external peripheral device.
2. Description of the Related Art
Conventionally, sequence control apparatuses are widely utilized as control apparatuses for industrial apparatuses. It should be understood that a sequence control apparatus corresponds to a control apparatus capable of sequentially performing control operations for industrial apparatuses at respective stages in accordance with a predetermined sequence in such a manner that the completion of one control operation is confirmed, and then the subsequent control operation is selected based upon the result of this control operation.
In the current sequence control apparatus, programmable controllers capable of changing programs (will be referred to as a "PC" hereinafter) constitute major controllers, and the contents of controlling operations are highly advanced. In recent years, while the external peripheral units are connected to PC, the ON/OFF conditions of the input/output signals in the external units controlled by PC, and also such information as numerical data stored within the CPU units can be monitored in real time on the CRT screens of the external peripheral units, for instance, personal computer and the like.
In the conventional PC, the major function is to monitor whether the input/output signal of the external unit under control is ON or OFF. However, in order to recognize the ON-time of the input/output signals which is required when the sequence program is debugged by the programmer, and the internal operating conditions such as the acquisition timings of the input/output signals, the user adds the debugging sequence program to the original sequence program, and activates this debugging sequence program so as to substitute the ON-time and internal operating conditions for the numerical data stored within the CPU unit. Then, these substituted numerical data may be monitored by the external peripheral unit, or may be measured by externally connecting a measuring apparatus such as a logic analyzer.
FIG. 45 is a schematic diagram showing the structure of this sort of conventional PC. In FIG. 45, reference numeral 1 indicates a PC unit functioning as a control center of this programmable controller, reference numeral 2 shows an external peripheral device for displaying a monitored result, and reference numeral 3 represents an input/output unit for fetching an input signal and also for supplying an output signal to external units under control such as a limit switch 4a, a lamp 4b, a valve controller 4c, and the like. Reference numeral 5 denotes a special function unit corresponding to a unit with a function for communicating with a computer 6 and the like.
Reference numerals 10 to 19 and 21 show various units provided within the CPU unit 1. Reference numeral 10 is a CPU (central processing unit) for executing a system program stored in a system ROM 12, reference numeral 11 indicates a sequence program memory for storing a sequence program, and reference numeral 13 represents a data RAM for temporarily storing data under execution of the CPU 10. Reference numeral 14 denotes a peripheral I/F (interface) used to communicate with the external peripheral unit 2, reference numeral 15 is an input/output port for transmitting/receiving a signal with the input/output unit 3, reference numeral 16 shows a device memory for storing conditions of the input/output signals used in the sequence program, and also the numeral data such as the present value of the timer, and reference numeral 17 indicates an interrupt producing circuit for producing a portion of the input/output signals as an interrupt signal. Reference numeral 18 represents an address comparing circuit for continuously monitoring the sequence program memory 11, and for issuing an interrupt to the CPU 10 when a preset address is made coincident with the designated address. Reference numeral 19 denotes a data comparing circuit for continuously monitoring the device memory 16, and for issuing an interrupt to the CPU 10 when a content of a preset address is made coincident with the designated data. The circuit configuration of the data comparing circuit 19 is identical to those disclosed in Japanese Unexamined Patent Publication Nos. Hei. 3-244003 and Hei. 4-151702. Reference numeral 21 denotes an internal timer that continues to measure time asynchronously with the operation of the CPU 10. Numeral 20 denotes a logic analyzer functioning as a measuring unit for monitoring an output signal during the debugging process of the sequence program to observe operating conditions of PC. The special function unit 5, the sequence program memory 11, the system RAM 12, the data RAM 13, the peripheral I/F 14, the input/output port 15, the device memory 16, the interrupt producing circuit 17, the address comparing circuit 18, and the data comparing circuit 19 are connected to the CPU 10 via various types of signal lines 10a such as an address signal line and a data signal line. The CPU 10 reads/writes the data with respect to the sequence program memory 11 and the like via the various sorts of signal lines 10a.
Next, a structure of the sequence program stored in the sequence program memory 11 shown in FIG. 45 will now be described, which is represented in FIG. 46. In FIG. 46, reference numeral 511 shows a main sequence program portion continuously executed, and reference numeral 512 indicates an interrupt sequence program executed only when an interrupt is issued from the interrupt producing circuit 17. Reference numeral 513 shows an FEND command indicative of completion of the main sequence program 511, reference numeral 514 shows an interrupt pointer indicative of commencement of the interrupt sequence program 512, and reference numeral 515 denotes an IRET command representative of completion of the interrupt program. Further, reference numerals 521 to 524 shown in FIG. 47 are instructions stated in the main sequence program 511 and the interrupt sequence program 512, by which the conditions of the external apparatuses of FIG. 45 to be controlled are read, or changed. In accordance with these instructions 521 to 524, the external apparatuses to be controlled are represented by the devices. For instance, a symbol "XO" of FIG. 49 (discussed later) contained in the instruction 521 implies an input signal derived from the external apparatus under the devices are, for example a bit device for storing ON/OFF conditions such as the input/output signals, a word device for storing numerical data, and a timer device. These conditions are stored in the device memory 16 of FIG. 45.
To execute the sequence program shown in FIG. 46, an example of the general execution process of the CPU unit 1 indicated in FIG. 45 is shown in FIG. 47 and will now be described. In FIG. 47, the CPU unit 1 first commences to execute the main program at a step 521. Then, the process operation is advanced to a step 522 at which a sequence process for executing the sequence control is performed. At a step 5221, the starting step of the sequence program is set to the head step, i.e., 0-step of the main sequence program based on the predetermined sequence program. At the next step 5222, the programs defined from the 0-step, namely starting step to the FEND command step are executed. When the FEND command is executed, the process operation is advanced to an END process step 523. At this step 523, a communication process step 5231 with the external peripheral unit 2, a special unit service process step 5232, and other END process step 5233 such as either input process, or output process of the input/output signals in accordance with the value stored in the device memory 16, are performed. When a series of END process step 523 is accomplished, the process operation is returned to the first step 522 at which the CPU unit 1 of FIG. 45 repeatedly performs the above-described process. As described above, it should be noted that the CPU unit 1 repeatedly executes the process operations defined at the steps 522 and 523, and a single process operation is referred to a "scan" in the specification.
The flow operation defined at the step 524 and the subsequent steps represents a flow operation to execute the interrupt program. This interrupt program is executed when the interrupt signal is inputted from the interrupt producing circuit 17 into the CPU 10 during the above-described repeating execution. When the interrupt program is commenced at the step 524, the execution step on the side of the main program presently executed at a step 5241 is saved. Next, at a step 5242, the starting step is set to the head step, namely a step of IO of the interrupt program. After the process operation has been performed up to the IRET command at a step 5243, the execution step of the main program is set to accomplish the execution of the interrupt program at a step 5244. The process operation is returned from the end step 5245 to the original main program. As described above, the CPU unit of FIG. 45 repeatedly performs the process operations of the normal main program defined at the steps 522 and 523, as represented in FIG. 47, and executes the interrupt program of the step 524 every time the interrupt process request is issued, and thereafter the process operation is returned to the main program.
Referring now to FIG. 47, a time chart for the process operations, indicated in FIG. 47, by the CPU unit 1 of FIG. 45 will be explained. In FIG. 48, reference numeral 531 indicates sequence process time required in the sequence process 522 shown in FIG. 47, which contains interrupt process 533 of the interrupt process 524 indicated in FIG. 47. Reference numeral 532 indicates END process time required in the END process 523 shown in FIG. 47. This END process time 532 is defined by combining communication process time 534 of the communication process 5231 with the external peripheral device 2 of FIG. 47, service process time 535 of the service process 5232 of the special function unit 5, and END process time 536 other than another END process 5233. It should be noted that time required for one scanning operation, namely communication between the sequence process time 531 and the END process time 532 will be referred to as "scan time" in this specification. That is to say, in FIG. 48, sequence process time 531a of the first scan time contains interrupt process time 533a and 533b, and END process time 532a contains communication process time 534a, service process time 535a, and other END process time 536a. Similarly, sequence process time 531b and END process time 532b which constitute the subsequent time contain various sorts of process time 533c, 533d, 534b, 535b, and 536b in accordance with contents of the process operations under execution.
As described above, the control of the conventional CPU 1 shown in FIG. 45 is to perform the repeating process operation as indicated in FIG. 47. In this case, for instance, when the computer 6 issues the processing request to the CPU unit 1, the CPU unit 1 recognizes it as the processing request derived from the special function unit 5 and performs the process operation via the special function unit 5. Then, the CPU unit 1 supplies this process result to the special function unit 5. Since the process 5232 of FIG. 47 responding to the request issued from this special function unit 5 is carried out during the END process 523, when the request is issued from the special function unit 5, the END process time 532 is temporarily increased. Also, since the execution process 524 of the interrupt program is performed when the interrupt is produced from the interrupt producing circuit 17 of FIG. 45, timing at which the interrupt program is executed and the times of execution are not constant, so that the sequence process time 531 of FIG. 48 is increased/decreased, depending on the sequence process time 531 of FIG. 48. As a result, the process time carried by the CPU unit 1 for every scan, which is constructed of the sequence process time 531 and the END process time 532 shown in FIG. 48, is not constant. Thus, the acquisition of the input signal and the output timing of the output signal become very complex. As described above, when the user would meet insufficient controls by the PC (programmable controller), this user should necessarily grasp the control conditions of the CPU unit 1 so as to check the reasons of such insufficient controls.
With reference to FIGS. 45 and 49, a description will now be made of a method for measuring changing time of a device condition, namely one of the control conditions of the CPU unit 1, for instance, a time duration during which the condition of the bit device X0 indicative of a certain input signal is ON. FIG. 49 schematically indicates one example of the sequence program used to measure the time duration during which the condition of the bit device X0 indicative of the input signal is ON. It should be noted that the bit device X0 corresponds to, for instance, an input signal of the limit switch 4a and the like in FIG. 45. In FIG. 49, reference numerals 541 to 543 indicate symbols of the respective commands. Reference numeral 541 shows a load command conducted when the bit device X0 is under ON state. Reference numeral 542 indicates a load negate command conducted when the bit device X0 is under OFF state. Reference numeral 543 is a timer command for commencing time measurement under conducting condition to store elapse time into the timer device, where K100 represents that a time period up to 1 second is measured. Reference numeral 544 indicates a transfer pulse command for storing the content of the timer device T0 into the word device D0 when the rising portion of the conducting state is detected.
Operations of the sequence program shown in FIG. 49 will now be described. That is, when the bit device X0 becomes ON, the load command 541 is conducted to activate the timer command 543, so that the contents of the timer device T0 are sequentially added by 1 every 10 ms. To the contrary, when the bit device X0 becomes OFF, the load negate command 542 is conducted so that the content of the timer device T0 corresponding to the present measurement time is stored into the device D0 in response to the transfer pulse command 544, and further the load command 541 becomes non-conductive, whereby the operation of the timer command 543 is stopped and the content of the timer device T0 becomes 0. The user adds this sequence program to the main sequence program so as to operate the CPU unit 1. As a result, the time period during which the bit device X0 is under ON state is continuously stored into the device D0, and therefore while the device condition of the device D0 is monitored by the outer peripheral unit 2, an interval between the condition changes may be detected. However, since the sequence program of FIG. 49 is executed every time the main program of the CPU unit 1 is repeatedly processed in accordance with this method, there are some possibilities that such an error of 1 scan time, namely the respective processing time period of the CPU unit 1, as previously explained in FIG. 48, may occur. Moreover, to achieve the current measurement, it is required to directly measure the input signal by the logic analyzer 20 shown in FIG. 45.
A description will now be made of another method for measuring the process time of the designated section of the sequence program, i.e., one of these control conditions of the CPU unit 1. The means for measuring the process time defined from the first step of the main sequence program until a certain designated step thereof during execution of the sequence process is described in Japanese Unexamined Patent Publication No. Hei. 5-189277. Thus, when measuring the process time for a certain designated section of the main sequence program during the execution of the sequence process, for instance the time to process the sequence program defined from the step 100 to the step 200, both of the execution process time up to the starting step of this designated section, namely from the step 0 to the step 100, and the execution process time up to the end step thereof, namely from the step 0 to the step 200 are measured by employing the above-described means. Then, the former execution process time up to the starting step is subtracted from the latter execution process time up to the end step, whereby the process time to execute the sequence program during the designated section, namely from the step 100 to the step 200 is calculated and then can be measured.
Referring now to FIGS. 45, 47 and 50, an explanation will be made as to a method for measuring the execution time of the interrupt sequence program corresponding to one of other control conditions by the CPU unit 1. FIG. 50 shows an example of a sequence program for measuring the process time of the interrupt sequence program 554. In this drawing, reference numeral 551 indicates a pointer IO indicative of the head of the interrupt sequence program 554, reference numeral 552 shows a load command which is conducted when the bit device M9036 is under ON state, and reference numerals 553, 557 show output commands for caucusing the bit device Y0 to be ON under conductive state, and for causing the bit device Y0 to be OFF under non-conductive state. Reference numeral 555 is a load negate command which is conducted when the bit device M9036 is under OFF state, and reference numeral 558 is an IRET command indicative of the end of the interrupt sequence program.
Operations of the sequence program represented in FIG. 50 will now be described. That is, when the interrupt program defined at the step 524 of FIG. 47 is executed, the load instruction 552 located at the beginning of the interrupt sequence program 554 of FIG. 50 is conducted, depending on the condition of the bit device M9036 which is continuously ON, and then the bit device Y0 is caused to be ON by the output command 553. The bit device Y0 is, for instance, the output signal from the lamp 5b. Subsequently, the originally provided interrupt sequence program 554 is executed, and the load negate command 555 just before the interrupt sequence program is brought into the non-conductive state, and the bit device Y0 is OFF. Then, the interrupt sequence program 554 is accomplished by the IRET command 558. As a consequence, this sequence program is added to the interrupt sequence program by the user so as to be operated by the CPU unit 1. Thus, while the interrupt sequence program is executed, the bit device Y0 is under ON state, and the output signal corresponding to this device Y0 is measured by using the logic analyzer 20 functioning as the external measuring device of FIG. 45, so that the execution time of the interrupt program can be acquired.
Referring now to FIG. 45, FIG. 47, FIG. 51, a description will be made of a method for measuring the execution time of the END process corresponding to one of other control conditions of the CPU unit 1. FIG. 51 is an example of a sequence program for measuring a time duration required to perform the END process. In FIG. 51, reference numeral 564 shows a main sequence program which should be in principle executed. Reference numeral 562 is a load negate command which is conducted when the bit device M9036 is under OFF state. Reference numerals 563 and 567 are output commands for causing the bit device Y0 to be ON under conductive state, and for causing the bit device Y0 to be OFF under non-conductive state. Reference numeral 565 shows a load command which is conducted when the bit device M9036 is under ON state. Reference numeral 568 is an FEND command indicative of the end of this main sequence program.
Now, operations of the sequence program shown in FIG. 51 will be explained. That is, when the process operation of the sequence process operation of FIG. 47 is executed, the load negate command 562 present at the beginning of the main sequence program 564 of FIG. 51 becomes non-conductive, depending upon the condition of the bit device M9036 which is continuously ON, and then the output command 553 causes the bit device Y0 to be OFF. Subsequently, the main sequence program 564 is executed, so that the load command 565 located just before the main sequence program is brought into the conductive state and the bit device Y0 is turned ON. Then, in response to the FEND command 568, the main sequence program 564 is accomplished. Thereafter, the process operation is advanced to a step 523 of the END process shown in FIG. 47, at which the sequence process at the step 522 is again executed. Then, the bit device Y0 is turned OFF and ON in a similar manner. While the main sequence program 564 is executed, the device Y0 is turned OFF by this repetition. While the device Y0 is turned ON, it is understood that the END process is carried out. As a result, the user adds this sequence program to the main sequence program to be operated by the CPU unit 1. Then, the output signal corresponding to this bit device Y0 is measured by utilizing the logic analyzer 20 functioning as the external measuring device of FIG. 45, so that the execution time for the END process and the execution time for the sequence process can be measured.
An explanation will now be made of a method for measuring the process time of the special unit service, corresponding to one of other control conditions of the CPU unit 1. In the method for measuring the process time of the special unit service, the method for measuring the execution time of the END process shown in FIG. 51, is employed as previously described. First, the process time of the END process 523 shown in FIG. 47 is measured under such condition that no request is issued from the special function unit 5 of FIG. 45. Next, the process time of the END process 523 is similarly measured under such condition that a request is issued from the special function unit 5. Then, the END process time measured when no request is issued from the special function unit 5, is subtracted from the END process time when the request is issued from the special function unit 5, whereby it is possible to obtain the process time of the END process 513 for the request issued from the special function unit 5.
With reference to FIG. 52, a description will now be made of a method for investigating how many times the interrupt sequence program is executed within a constant time period, corresponding to one of other control conditions of the CPU unit 1. FIG. 52 shows one example of a sequence program for measuring the execution times of interrupt sequence program. In FIG. 52, reference numerals 571 and 577 are load instructions which are conducted when the bit device M9036 is under ON state. Reference numerals 572 and 576 denote output commands for outputting the conductive condition to the bit device M0. Reference numeral 573 indicates a transfer command for storing the constant "0" to the content of the word device D0 under conductive condition. Reference numeral 574 shows the original main sequence program. Reference numeral 575 is a load negate command which is conducted when the bit device M9036 is under OFF state. Reference numeral 578 is a transfer command for storing the content of the word device D0 into the content of the word device D1 under conductive condition. Reference numeral 579 shows an FEND command indicative of an end of the main sequence program 574. Reference numeral 5710 is a pointer representative of a head of the interrupt sequence program 5711. Reference numeral 5711 shows the original interrupt program. Reference numeral 5712 is a load instruction which becomes conductive when the bit device M0 is under ON state. Reference numeral 5713 is an adding command for adding 1 to the content of the word device D0 under conductive state. Reference numeral 5714 is an IRET command for indicating an end of the interrupt sequence program.
In the example shown in FIG. 52, such a measurement is carried out based on the number of times the interrupt sequence program subsequent to the interrupt pointer (IO) 5710 is performed within the time duration during which the main sequence program is performed one time. This sequence program is operated as follows. At the beginning, both the load command 571 and the output command 572 cause the bit device M0 to be turned ON, and the transfer command 573 causes the content of the word device D0 to be 0. Subsequently, the original main sequence program is executed, and both the load negate command 575 and the output command 576 cause the bit device M0 to be turned OFF. When the interrupt sequence program 5711, after the interrupt point (IO) 5710 as the interrupt process, is performed during the above-described operation, if the bit device M0 is turned ON by the load instruction 5712 and the adding instruction 5713, then the content of the word device D0 is incremented by 1, and also the execution of the interrupt sequence program 5711 is accomplished in response to the IRET command 5714. Accordingly, since the bit device M0 is turned ON while the main sequence program 574 is executed, the execution times of the interrupt sequence program 5711 subsequent to the interrupt pointer (IO) 5710, which has been executed during this ON time period, are stored into the content of the word device D0. This value is transferred to the content of the word device D1 in response to the load instruction 577 and the transfer instruction 578. As a consequence, the user adds this sequence program to the sequence program which is operated by the CPU unit 1, and also the content of this word device D1 is monitored by employing the external peripheral unit 2, so that it could be recognized how many times the interrupt sequence program subsequent to the interrupt pointer (IO) 5710 has been executed while the main sequence program is performed one time.
Next, the execution times of the service process in response to the processing request issued from the special unit 5 could not be measured by adding the sequence program.
Referring to FIGS. 45, 47 and 53, a description will now be made of a method for measuring interval time of starting the execution of the interrupt sequence program, corresponding to one of other control conditions of the CPU unit 1. FIG. 53 shows an example of a sequence program for measuring the interval time of starting of the execution of the interrupt sequence program. In this drawing, reference numeral 551 indicates a pointer IO indicative of the head of the interrupt sequence program 554, reference numeral 582 shows a load command which is conducted when the bit device M9036 is under ON state, and reference numeral 583 indicates a transfer command for storing the content of the word device D9022 into the word device D0 under conductive condition. Reference numeral 584 is a subtraction command for subtracting the content of the word device D1 from the content of the word device D0 under conductive condition to store the subtracted value into the word device D2. Reference numeral 585 shows a transfer command for storing the content of the word device D0 into the word device D1 under conductive condition. Reference numeral 586 is the original interrupt sequence program, and reference numeral 587 is an IRET command indicative of an end of the interrupt sequence program 586. In response to the transfer command 583, the content of the word device D9022 for transfer destination is incremented by 1 by the CPU 10 every 1 second.
Operations of the sequence program shown in FIG. 53 will now be described. That is, in response to the load command 582 and the transfer command 583, the content of the word device D9022 corresponding to the count value of the counter at this time is saved to the word device D0. Then, in accordance with the subtraction instruction 584, the content of the word device D1 into which the count value at the preceding interrupt has been stored is subtracted from the content of the word device D0. The subtraction result is stored into the word device D2. Then, in response to the transfer command 585, the saved content of the word device D0 is stored into the word device D1 to be used during the next interrupt. As a result, the user adds this sequence program to the interrupt sequence program to be operated by the CPU unit 1, so that the interval time of starting the execution of the interrupt sequence program in unit of 1 second is stored into the word device D2 every time the interrupt sequence program subsequent to the interrupt pointer IO is performed. Accordingly, the interval time of starting the execution of the interrupt sequence program 587 could be obtained by monitoring the content of the word device D2 by way of the external peripheral device 2.
A method for measuring an interval of executing a process operation when a request is issued from the special function unit 5, corresponding to one of other control conditions of the CPU unit 1 will now be described with reference to FIG. 45 and FIG. 54. FIG. 54 shows an example of a sequence program for measuring the time interval of executing the process operation when the request is made from the special function unit 5 of FIG. 45. Here, reference numeral 592 shows a load command which is conducted when the bit device Y1E is under ON state, and reference numeral 593 denotes a transfer pulse command for storing the content of the word device D9022 into the word device D0 when the rising portion of the conductive condition is detected. Reference numeral 594 is a subtraction pulse command for subtracting the content of the word device D1 from the content of the word device D0 when the rising portion of the conductive condition is detected, and for storing the subtraction result into the word device D2. Reference number 595 shows a transfer pulse command for storing the content of the word device D0 into the word device D1 when the rising portion of the conductive condition is detected. Reference numeral 596 is the original interrupt sequence program. Reference numeral 597 shows an IRET instruction for indicating a completion of the interrupt sequence program 596. It should be noted that the bit device Y1E of the load instruction 592 corresponds to such a bit device which is ON when the request is issued from the special function unit 5, and the content of the word device D9022 to which the transfer pulse command 593 is transferred is incremented by 1 by the CPU 10 every one second.
Operations of the sequence program indicated in FIG. 54 will now be explained. That is, in response to the load command 592 and the transfer pulse command 593, when the request is issued from the special function unit 5 of FIG. 45, the content of the word device D9022 functioning as the counter at this time is saved to the word device D0. Then, in accordance with the subtraction pulse command 594, the content of the word device D1 into which the count value when the request was issued from the special function unit 5 at the previous execution has been stored is subtracted from the word device D0. The subtraction result is stored into the word device D2. In response to the transfer pulse command 595, the content of the saved word device D0 is stored into the word device D1 which will be used when another request is issued from the special function unit at the next time. As a consequence, when this sequence program is added to the main program by the user to be operated by the CPU unit 1, if the request is issued from the special function unit 5, then this sequence program 596 is performed, and the interval time of the requests issued from the special function unit 5 in unit of 1 second is stored into the word device D2. Therefore, the content of the word device D2 is monitored by the external peripheral unit 2, so that the interval time of the request issued from the special function unit 5 could be measured.
Since the programmable controller directly controls such high speed operating machines as motors and robots, it is very important to detect delicate timings of the signals. When extraordinary operation happens to occur in the actual location, the reason for this extraordinary operation should be immediately investigated. However, in accordance with the above-described conventional method, the sequence program to detect timings must be added. It is not practically preferable to modify the program of the system under operation.
Also, the method for grasping the internal operation condition which is effected when the sequence program is debugged by the programmer cannot be easily achieved, because the debugging sequence program is added to be executed. Further, there are some possibilities that the operation conditions of the CPU are differed from each other. There is another problem that an external measuring device is needed in the method of using the external measuring device.
In addition, there is another problem that since the execution time of the processing request issued from the special function unit 5 within a constant time cannot be measured, the detailed operation condition of PC cannot be recognized. To measure the time required to perform the process operation by the CPU unit 1 in response to the request from the special function unit 5, the time measuring sequence program may be established by the user. In this case, since the initiation signal from the special unit 5 is fetched into the CPU unit 1 during the END process of the sequence program, precision in the actual initiating interval time is deteriorate, so that cumbersome programming works of the user are required.
The data comparing circuit 19 of FIG. 45 is disclosed in Japanese Unexamined Patent Publication Nos. Hei. 3-244003 and Hei. 4-151702. However, this data comparing circuit is only used to stop the operation and lock the data when the content of the device memory is under designation, but is not used to detect the time intervals under ON-line condition.
To measure the process time of a certain designated section of the sequence program under execution of the sequence process, the interrupt is issued at two steps within the designated section, namely the starting step and the end step, under execution of the sequence process. As a result, more than two sets of address comparing circuits 18 shown in FIG. 45 for producing the interrupt at an arbitrary step are required.
As to the execution time of the interrupt program, very recently, the high speed control apparatuses have become available. There are many cases that the interrupt program is used as the process operation with the higher priority which requires the high speed characteristics. It is a very important factor in the system design to achieve balance between the overall control performance of the main program and the interrupt program. However, since the total time of the execution time for the main program and the execution time for the interrupt program is detected as the scan time in the conventional method, it is difficult to judge whether the lengthy scan time is caused by executing the main program itself, or by executing the interrupt program when the scan time exceeds predicted time. When the initiating interval of the interrupt program is measured by the program shown as in FIG. 53 by the user, this ladder program must be inserted into the head of the interrupt program. When the quantity of the interrupt program is increased, there is another problem that the programming work by the user becomes cumbersome. Furthermore, there is a further problem that the actual processing time of the interrupt program would be prolonged since these processes are executed on the ladder program.